blob: 32352b5ed97e698b9e62a835d3d7e9268c485ee4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
|
/**
* @file
*
* @ingroup lpc32xx_mmu
*
* @brief MMU support API.
*/
/*
* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_ARM_LPC32XX_MMU_H
#define LIBBSP_ARM_LPC32XX_MMU_H
#include <libcpu/arm-cp15.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @defgroup lpc32xx_mmu MMU Support
*
* @ingroup arm_lpc32xx
*
* @brief MMU support.
*
* @{
*/
#define LPC32XX_MMU_CLIENT_DOMAIN 15U
#define LPC32XX_MMU_READ_ONLY \
((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
| ARM_MMU_SECT_DEFAULT)
#define LPC32XX_MMU_READ_ONLY_CACHED \
(LPC32XX_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
#define LPC32XX_MMU_READ_WRITE \
((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
| ARM_MMU_SECT_AP_0 \
| ARM_MMU_SECT_DEFAULT)
#define LPC32XX_MMU_READ_WRITE_CACHED \
(LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
/**
* @brief Sets the @a section_flags for the address range [@a begin, @a end).
*
* @return Previous section flags of the first modified entry.
*/
static inline uint32_t lpc32xx_set_translation_table_entries(
const void *begin,
const void *end,
uint32_t section_flags
)
{
return arm_cp15_set_translation_table_entries(begin, end, section_flags);
}
/** @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_LPC32XX_MMU_H */
|