Age | Commit message (Collapse) | Author |
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The shared memory base is normally set by the user application. It
defaults to 0x40000000 for LEON3 (start of memory) since before,
with GR740 having its memory at 0x00000000 a better base address
the new default is to based it on the _RAM_START taken from the
linker script.
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The RTEMS MP test-suite was originally designed to two identical nodes,
however the LEON devices is often operating several instances of the
RTEMS MP configuration wihtin the same device sharing memory.
Therefore this places the RTEMS MP nodes at different RAM location.
The node1.exe and node2.exe can be started from GRMON like this on a GR712RC
with 4MiB SRAM:
grmon> cpu act 0
grmon> load build/sparc-gaisler-rtems5/c/gr712rc_mp/testsuites/mptests/mp01_node1.exe cpu0
grmon> stack 0x401ffff0 cpu0
grmon> load build/sparc-gaisler-rtems5/c/gr712rc_mp/testsuites/mptests/mp01_node2.exe cpu1
grmon> stack 0x403ffff0 cpu1
grmon> run
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There is no need for two device drivers for the same IP. Old applications
should migrate to using the newer GRSPW packet driver (grspw_pkt.c) which
has a much more flexible interface, more functions with a better zero-copy
API and is actively maintained. All LEON devices and SpW IP from Gaisler
are supported by the GRSPW Packet driver.
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Provide a BSP specific default RTEMS configuration mainly intended
to simplify for POSIX targets bring-up
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The errata is worked around in the kernel without requiring toolchain
modifications. It is triggered the JMPL/RETT return from trap instruction
sequence never generated by the compiler and. There are also other
conditions that must must be true to trigger the errata, for example the
instruction that the trap returns to has to be a JMPL instruction. The
errata can only be triggered if certain data is corrected by ECC
(inflicted by radiation), thus it can not be triggered under normal
operation. For more information see:
www.gaisler.com/notes
Affected RTEMS target BSPs:
* GR712RC
* UT699
* UT700/699E
The work around is enabled by defining __FIX_LEON3_TN0018 at build time.
In general there are two approaches that the workaround uses:
A) avoid ECC restarting the RETT instruction
B) avoid returning from trap to a JMPL instruction
Where A) comes at a higher performance cost than B), so B) is used
where posssible. B) can be achived for certain returns from trap
handlers if trap entry is controlled by assembly, such as system calls.
A)
A special JMPL/RETT sequence where instruction cache is disabled
temporarily to avoid RETT containing ECC errors, and reading of RETT
source registers to "clean" them from incorrect ECC just before RETT
is executed.
B)
The work around prevents JMPL after system calls (TA instruction) and
modifies assembly code on return from traps jumping back to application
code. Note that for some traps the trapped instruction is always
re-executed and can therefore not trigger the errata, for example the
SAVE instruction causing window overflow or an float instruction causing
FPU disabled trap.
RTEMS SPARC traps workaround implementation:
NAME NOTE TRAP COMMENT
* window overflow 1 - 0x05 always returns to a SAVE
* window underflow 1 - 0x06 always returns to a RESTORE
* interrupt traps 2 - 0x10..1f special rett sequence workaround
* syscall 3 - 0x80 shutdown system - never returns
* ABI flush windows 2 - 0x83 special rett sequence workaround
* syscall_irqdis 4 - 0x89
* syscall_irqen 4 - 0x8A
* syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction
* syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to
B) _Internal_error() starting with SAVE
Notes:
1) no workaround needed because trap always returns to non-JMPL instruction
2) workaround implemented by special rett sequence
3) no workaround needed because system call never returns
4) workaround implemented by inserting NOP in system call generation. Thus
fall into 1) when workaround is enabled and no trap handler fix needed.
5) trap handler branches into both 1) and returning to _Internal_error()
which starts with a SAVE and besides since it shuts down the system that
RETT should never be in cache (only executed once) so fix not necessary
in this case.
Any custom trap handlers may also have to be updated. To simplify that,
helper work around assembly code in macros are available in a separate
include file <libcpu/grlib-tn-0018.h>.
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Not used by the driver itself, but shuold be correct if used by
application.
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This commit fixes an issue when booting SMP application: entry point can become
invalid for secondary processors.
The first CPU does the following in the boot_card():
1. Release other CPUs from power-down (but does not wait here)
2. Some other stuff
3. Overwrite trap entry 0 with spurious interrupt handler.
4. The rest
It means that the entry point is guaranteed to be valid for the first CPU
entering the RTEMS kernel. But 1. and 3. above gives a race. CPU1.. will either
enter the kernel properly or end up in the spurious interrupt handler depending
on how soon it reaches the entry point it is.
One example where this has been an issue is when secondary processors run
self-tests in a ROM boot loader before entering the RTEMS entry point.
"start" is trap entry 0 in the trap table and directly jumps to "hard_reset".
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Allows user to set SpaceWire run clock divisor for an individual port.
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dl10 test actually works when the appropriate input is given,
however the test frame work is not capable of doing this and
check agains .scn file.
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Without this smp05 and smpthreadlife01 tests may fail
depending on how the boot loader initialized the GPTIMER.
Before the time counter stopped counting when reaching
zero, but tests could work since it could take 2^32 us
before stopping.
The timer driver will potentially overwrite this, but it
happens later due to the initialization order having
RTEMS_SYSINIT_CPU_COUNTER very early.
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Moves drvmgr_drivers[] from amba.c to a separate file in order
to avoid the dependecy on APBUART/GPTIMER drivers. This has
an effect when user configured not to use timer or uart
in their project.
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The descriptor table size is equal to its alignment and set when
configuring the HW IP through VHDL generics. This SW patch simply
probes the HW how large the RX/TX descriptor tables are and adjusts
accordingly.
The number of descriptors actual used are controlled by other
settings (rxDescs and txDescs) controlled by the user.
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The new GRCAN_FD IP supports CAN FD standard and is mostly backwards
compatible with GRCAN SW interface. The GRCAN driver have been extended
to support the GRCANFD IP using the same driver.
Additional functions have been added that uses a new CAN FD frame
format and read/write/baud-rate functions that supports both GRCANFD
and GRCAN. To keep the SW API fully backwards compatible with GRCAN,
the old functions remain.
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Reimplemented the baud-rate algorithm from scratch to cope with
GRCAN, GRCANFD and OC_CAN devices.
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When the DMA table has been allocated dynamically, the IOCTL_SET_PACKETSIZE
will trigger an issue where pDev->rx and pDev->tx are not updated with
the new DMA tables base address. Instead the old pointers are used.
There is no point in reallocting the DMA tables because there is no
configuration option to it. Therefore the DMA tables allocation is
moved to a separate function never called from SET_PACKETSIZE.
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This is enables the updated codec for GR740 and is backwards compatible
with all other versions of the IP.
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malloc04 and malloctest tests from the rtems test-suite fails
when checking the return value of malloc(). The check is
optimized away and always fails.
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It seems not to be possible to disable tests based on toolchain or any
other if condition or configure (--disable-test-N or similar). Even though
it is working on GCC it is temporarily disabled her.
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The C11 standard definition of atomic_load do not accept const pointers. This
appear to be a deficiency in the C11 standard. It looks like a fix is
underway/has applied as per:
http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_459.htm
While GCC do allow const pointers to atomic_load Clang does not. To
compile with Clang we therefore need to remove the const qualifiers.
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Disable dl06 test that does not currently build
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For compatibility with non-FPU targets.
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The flat register window model activated by -mflat is ABI
compatible with the standard SPARC ABI.
SAVE/RESTORE instructions are not generated by the compiler.
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