From 40599e7e86f29acd422124223e1758fea7beaa63 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 5 Jun 2014 10:01:42 +0200 Subject: bsps/arm: Change L2 cache initialization Do not touch the L1 caches since they have been initialized by the start hooks. --- c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4 +- c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 47 ---------------------- 2 files changed, 1 insertion(+), 50 deletions(-) diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h index 5e5ef6df4d..577fd2f2e2 100644 --- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h +++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h @@ -1361,7 +1361,6 @@ static inline void _CPU_cache_enable_data( void ) { cache_l2c_310_enable(); - arm_cache_l1_enable_data(); } static inline void @@ -1375,7 +1374,6 @@ static inline void _CPU_cache_enable_instruction( void ) { cache_l2c_310_enable(); - arm_cache_l1_enable_instruction(); } static inline void @@ -1590,4 +1588,4 @@ _CPU_cache_get_instruction_cache_size( const uint32_t level ) } #endif /* __cplusplus */ -#endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */ \ No newline at end of file +#endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */ diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 10f680d1ea..139c17182e 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -352,28 +352,6 @@ static inline void arm_cache_l1_unfreeze_instruction( void ) /* To be implemented as needed, if supported by hardware at all */ } -static inline void arm_cache_l1_enable_data( void ) -{ - uint32_t ctrl; - - arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); - - assert( ARM_CACHE_L1_CPU_DATA_ALIGNMENT == arm_cp15_get_data_cache_line_size() ); - - ctrl = arm_cp15_get_control(); - - /* Only enable the cache if it is disabled */ - if ( !( ctrl & ARM_CP15_CTRL_C ) ) { - /* Clean and invalidate the Data cache */ - arm_cache_l1_invalidate_entire_data(); - - /* Enable the Data cache */ - ctrl |= ARM_CP15_CTRL_C; - - arm_cp15_set_control( ctrl ); - } -} - static inline void arm_cache_l1_disable_data( void ) { /* Clean and invalidate the Data cache */ @@ -395,31 +373,6 @@ static inline void arm_cache_l1_disable_instruction( void ) arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I ); } -static inline void arm_cache_l1_enable_instruction( void ) -{ - uint32_t ctrl; - - arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); - - assert( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT - == arm_cp15_get_data_cache_line_size() ); - - /* Enable Instruction cache only if it is disabled */ - ctrl = arm_cp15_get_control(); - - if ( !( ctrl & ARM_CP15_CTRL_I ) ) { - /* Invalidate the Instruction cache */ - arm_cache_l1_invalidate_entire_instruction(); - - /* Enable the Instruction cache */ - ctrl |= ARM_CP15_CTRL_I; - - arm_cp15_set_control( ctrl ); - } - - arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); -} - static inline size_t arm_cache_l1_get_data_cache_size( void ) { size_t size; -- cgit v1.2.3