From 283f783d5d884c0f0f823c5f2d24ebaa97624d88 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 11 Mar 2024 14:18:46 +0100 Subject: aarch64/zynqmp: Fix UART base addresses and IRQ The base addresses and IRQ numbers for UART 0 and 1 were interchanged. Fix this and set BSP_CONSOLE_MINOR to 0 for this BSP family. --- bsps/aarch64/xilinx-zynqmp/console/console.c | 4 ++-- bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h | 4 ++-- spec/build/bsps/optconminor.yml | 1 + 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c b/bsps/aarch64/xilinx-zynqmp/console/console.c index 0b62893e67..9ce0b1da63 100644 --- a/bsps/aarch64/xilinx-zynqmp/console/console.c +++ b/bsps/aarch64/xilinx-zynqmp/console/console.c @@ -187,11 +187,11 @@ RTEMS_SYSINIT_ITEM( static zynq_uart_context zynqmp_uart_instances[2] = { { .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ), - .regs = (volatile struct zynq_uart *) 0xff010000, + .regs = (volatile struct zynq_uart *) 0xff000000, .irq = ZYNQMP_IRQ_UART_0 }, { .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ), - .regs = (volatile struct zynq_uart *) 0xff000000, + .regs = (volatile struct zynq_uart *) 0xff010000, .irq = ZYNQMP_IRQ_UART_1 } }; diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h index 2cbe99f863..024fd0d89a 100644 --- a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h +++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h @@ -56,8 +56,8 @@ extern "C" { #define ZYNQMP_IRQ_QSPI 47 #define ZYNQMP_IRQ_I2C_0 49 #define ZYNQMP_IRQ_I2C_1 50 -#define ZYNQMP_IRQ_UART_0 54 -#define ZYNQMP_IRQ_UART_1 53 +#define ZYNQMP_IRQ_UART_0 53 +#define ZYNQMP_IRQ_UART_1 54 #define ZYNQMP_IRQ_ETHERNET_0 89 #define ZYNQMP_IRQ_ETHERNET_1 91 #define ZYNQMP_IRQ_ETHERNET_2 93 diff --git a/spec/build/bsps/optconminor.yml b/spec/build/bsps/optconminor.yml index 514b3fa032..3f17f05fe7 100644 --- a/spec/build/bsps/optconminor.yml +++ b/spec/build/bsps/optconminor.yml @@ -7,6 +7,7 @@ copyrights: - Copyright (C) 2020 embedded brains GmbH & Co. KG default: - enabled-by: + - aarch64/bsps/xilinx-zynqmp - arm/xilinx_zynq_microzed value: 0 - enabled-by: true -- cgit v1.2.3