| Age | Commit message (Collapse) | Author |
|---|
|
Place the vector table in the start section so that the overlay can be
avoided if we execute from internal flash. The problem is that when the
POM is enabled, the ECC cannot be enabled for the internal flash.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Replace TMS570_MMR_SELECT_GMII_SEL with TMS570_MMR_SELECT_MII_MODE and
TMS570_MMR_SELECT_RMII_MODE.
|
|
Rearrange pin function bit fields to allow the clearing of all function
bits through TMS570_PIN_AND_FNC().
Move implementation details to source file.
|
|
|
|
|
|
Add the BSP option BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENT to
optionally define an alignment of the vector address table begin.
|
|
|
|
This patch adds basic support for the following boards:
xilinx_zynq_pynq - PYNQ Z1 / Z2
xilinx_zynq_microzed - MicroZed 7010 / 7020
xilinx_zynq_picozed - PicoZed 7010 / 7015 / 7020 / 7030
xilinx_zynq_zybo - ZYBO
xilinx_zynq_zybo_z7 - ZYBO Z7-10 / Z7-20
N.b. Arty Z7-20 is basically a PYNQ Z1 - different board
color and updated Eth PHY.
|
|
|
|
|
|
This helps to validate that the data was transferred correctly.
|
|
Close #4971.
|
|
This can be used to report that nested test cases did run in a test
case.
Update #4971.
|
|
The pinctrl-0 of the video_mux might overwrite pin settings done by
other peripherals. Disabling it by default prevents unexpected pin
settings.
|
|
With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
|
|
Device trees allow mixing different kinds of GPIOs in one property. For
that it is usefull to only provide a pointer to an arbitrary location in
the property and initialize a GPIO from that.
|
|
Update #3716.
|
|
For uniprocessor configurations, the selection of
RTEMS_MULTIPROCESSOR_RESOURCE_SHARING results in a priority ceiling
mutex.
Build the MrsP validation tests only if RTEMS_SMP is enabled.
Update #3716.
|
|
Updates #4968
|
|
|
|
|
|
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
|
|
|
|
Update #3716.
|
|
The goal is to get code and branch coverage from actual tests and not
the test support itself.
|
|
|
|
The code coverage build is usually done without compiler optimizations.
This results in long performance test runtimes and useless performance
results.
|
|
Test some compiler builtins which may use integer library routines:
https://gcc.gnu.org/onlinedocs/gccint/Integer-library-routines.html
Update #3716.
|
|
|
|
Enable an individual testsuite only through the corresponding enable.
Use BUILD_TESTS to change the default value of the individual testsuite
enable options. This allows the user to enable all testsuites with
specific exceptions.
For example, this builds all testsuites except the benchmarks:
[arch/bsp]
BUILD_TESTS = True
BUILD_BENCHMARKS = False
|
|
Change the public image data type to a void pointer.
|
|
|
|
Thread_Life_state is used as a bitfield, but is declared as an enum.
This converts the enum typedef to a uint32_t typedef and associated bit
definitions.
|
|
The xnandpsu driver conditionally tries to wrap page index to NAND chip
size causing an off-by-one error where the first page of the second chip
is not wrapped correctly. This removes the conditional so that page
index is always wrapped.
|
|
On configurations where multiple NAND chips are in use, the erasure
loop in XNandPsu_Erase() can reset the loop counter variable once it
gets to blocks in the second chip causing an infinite loop overwriting
parts of the first chip. This change ensures that the loop counter is
not accidentally reset.
|
|
Prefer use of XNandPsu_Erase instead of XNandPsu_EraseBlock since the
XNandPsu driver does not expose the primitives necessary to ensure
device readiness after the operation is complete.
|
|
This adds a MicroBlaze-specific bsp_interrupt_dispatch wrapper which
fixes a linker error.
|
|
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
|
|
This imports Xilinx support code for the MPU and cache on Cortex-R5
cores. This was imported as specified in bsps/shared/xil/VERSION.
|
|
Replace the main page with a high level description of the RTEMS feature
set similar to:
https://docs.rtems.org/branches/master/user/overview/index.html#features
The replaced content can be found in the RTEMS Classic API Guide:
https://docs.rtems.org/branches/master/c-user/overview.html
https://docs.rtems.org/branches/master/c-user/key_concepts.html
Update #3705.
|
|
If used with the format-and-define action, this will result in an
undefined define.
|
|
This fixes a build error with RTEMS_PROFILING enabled.
Update #4954.
|
|
Close #4954.
|
|
Simplify leon3_counter_use_irqamp_timestamp().
Update #4954.
|
