blob: b573d3c7d9f8a7b45dafb50e7fc19bce70c2fea8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
/**
* @file
*
* MIPS Tx3904 specific information
*
* NOTE: This is far from complete. --joel (13 Dec 2000)
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __TX3904_h
#define __TX3904_h
/*
* Timer Base Addresses and Offsets
*/
#define TX3904_TIMER0_BASE 0xFFFFF000
#define TX3904_TIMER1_BASE 0xFFFFF100
#define TX3904_TIMER2_BASE 0xFFFFF200
#define TX3904_TIMER_TCR 0x00
#define TX3904_TIMER_TISR 0x04
#define TX3904_TIMER_CPRA 0x08
#define TX3904_TIMER_CPRB 0x0C
#define TX3904_TIMER_ITMR 0x10
#define TX3904_TIMER_CCDR 0x20
#define TX3904_TIMER_PGMR 0x30
#define TX3904_TIMER_WTMR 0x40
#define TX3904_TIMER_TRR 0xF0
#define TX3904_TIMER_READ( _base, _register ) \
*((volatile uint32_t*)((_base) + (_register)))
#define TX3904_TIMER_WRITE( _base, _register, _value ) \
*((volatile uint32_t*)((_base) + (_register))) = (_value)
#endif
|