| Age | Commit message (Collapse) | Author |
|---|
|
Also fix missing include directory required by beagle for the testsuite.
|
|
Unlike the older build this keeps files within each BSP now that we have a
one-directory-per-bsp model.
This supports external BSPs trivially by keeping all files separate from
the base build.
|
|
|
|
Update #3818.
|
|
Update #3818.
|
|
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
Update #3785.
|
|
|
|
Always provide this function. Return 0 by default. Fix formatting.
Simplify function.
Update #3785.
|
|
|
|
The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.
Enable it by default on the realview_pbx_a9_qemu BSP.
|
|
|
|
|
|
|
|
ld.lld defaults .work to PROGBITS otherwise
|
|
LLVM/LLD does not support STARTUP and ALIGN_WITH_INPUT directives that
GNU LD support. INPUT and ALIGN(8) are supported by LLVM/LLD and can
replace the unsupported STARTUP/ALIGN_WITH_INPUT directives.
The commit conditionally adds the supported directive that linkers
can understand depending on the toolchain used to compile RTEMS
i.e., clang or gcc. Clang is assumed to use LLD by default.
|
|
This commit moves the existing linkcmds.base to linkcmds.base.in
in order to make it configurable by autotools.
|
|
Use NULL-pointer protection also for Qemu variant.
Do all calculations in the linker command file. This is a preparation
for the new build system.
|
|
Do all calculations in the linker command file. This is a preparation
for the new build system.
|
|
This allows to mix SC16IS752 chips with other interrupts.
|
|
|
|
For level triggered interrupts currently the handler would have been
called two times (assuming no one cleared the mask in a handler which
would have been bad because the handler couldn't process all other that
got cleared by accident). This patch allows the handler only to return
if nothing is left to do.
|
|
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
|
|
|
|
Add support for _SMP_Send_message() to the own processor. This is
required by the smpmulticast01 test program.
|
|
The use case for this function is the libbsd. In FreeBSD, the interrupt
setup and binding to a processor is done in two steps. Message
based interrupts like PCIe MSI and MSI-X interrupts can be implemented
through interrupt server entries. They are setup at the default
interrupt server and may optionally move to an interrupt server bound to
a specific processor.
|
|
|
|
Directly use the CPU port API in boot_card() to allow tracing of the
higher level interrupt disable/enable routines, e.g.
_ISR_Local_disable() and _ISR_Local_enable(). Currently, there is no
configuration option to enable this. Below is a patch. It may be used
to investigate some nasty low level bugs in the system.
Update #3665.
diff --git a/cpukit/include/rtems/score/isrlevel.h b/cpukit/include/rtems/score/isrlevel.h
index c42451d010..46d361ddc2 100644
--- a/cpukit/include/rtems/score/isrlevel.h
+++ b/cpukit/include/rtems/score/isrlevel.h
@@ -40,6 +40,10 @@ extern "C" {
*/
typedef uint32_t ISR_Level;
+uint32_t rtems_record_interrupt_disable( void );
+
+void rtems_record_interrupt_enable( uint32_t level );
+
/**
* @brief Disables interrupts on this processor.
*
@@ -56,8 +60,7 @@ typedef uint32_t ISR_Level;
*/
#define _ISR_Local_disable( _level ) \
do { \
- _CPU_ISR_Disable( _level ); \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
+ _level = rtems_record_interrupt_disable(); \
} while (0)
/**
@@ -72,10 +75,7 @@ typedef uint32_t ISR_Level;
* _ISR_Local_disable().
*/
#define _ISR_Local_enable( _level ) \
- do { \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- _CPU_ISR_Enable( _level ); \
- } while (0)
+ rtems_record_interrupt_enable( _level )
/**
* @brief Temporarily enables interrupts on this processor.
@@ -98,9 +98,8 @@ typedef uint32_t ISR_Level;
*/
#define _ISR_Local_flash( _level ) \
do { \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- _CPU_ISR_Flash( _level ); \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
+ rtems_record_interrupt_enable( _level ); \
+ _level = rtems_record_interrupt_disable(); \
} while (0)
/
|
|
- The TI's CortexA7 MP MPIDR register returns 0
Updates #3760
|
|
- Update the linkcmd file to support configure settings
- Set the workspace size based on the revision value
|
|
Closes #3777
|
|
Closes #3780
|
|
Remove static stuff that is never used.
|
|
- Port the jbang code from C++ to C to enable DBGEN.
- Hook the libdebugger ARM backend support to return the base address
of the debug register set.
|
|
Closes #3760
|
|
Add NULL-pointer protection. Make MMU table read-only. Move vector
table to start section.
Close #3774.
|
|
|
|
This fixes the corruption of r3 by the call to
bsp_start_arm_drop_hyp_mode().
Moving the code makes it easier to review changes in start.S.
Close #3773.
|
|
This makes it easier to review changes in start.S.
Update #3773.
|
|
There are no known ARMv7-M chips with a dual lockstep mode.
Update #3773.
|
|
Update #3269.
|
|
The old driver worked well for EEPROMS with the RTEMS EEPROM driver. But
it had problems with a lot of other situations. Although it's not a
direct port, the new driver is heavily modeled after the FreeBSD ti_i2c
driver.
Closes #3764.
|
|
Closes #3762
|
|
Fix the __size symbol value to reflect the total size of the bootloader.
This prevents a bootloader crash with application images above a certain
threshold (e.g. fileio sample program).
Update #3727.
|
|
|
