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authorDaniel Hellstrom <daniel@gaisler.com>2020-05-14 13:48:25 +0200
committerDaniel Hellstrom <daniel@gaisler.com>2020-05-14 21:37:15 +0200
commit97f2de66e1ecb3ad06476dd01e2ca484e11c1de9 (patch)
treecceb76ced10fcdbe8e711075d265f0399a737f50 /cpukit/score/cpu/sparc/Makefile.am
parent09bd9afdfdeebf8b9d3fb58d0043e74c4dccd491 (diff)
leon,tn-0018: work around GRLIB-TN-0018 erratarcc-v1.2.24rcc-1.2
The errata is worked around in the kernel without requiring toolchain modifications. It is triggered the JMPL/RETT return from trap instruction sequence never generated by the compiler and. There are also other conditions that must must be true to trigger the errata, for example the instruction that the trap returns to has to be a JMPL instruction. The errata can only be triggered if certain data is corrected by ECC (inflicted by radiation), thus it can not be triggered under normal operation. For more information see: www.gaisler.com/notes Affected RTEMS target BSPs: * GR712RC * UT699 * UT700/699E The work around is enabled by defining __FIX_LEON3_TN0018 at build time for the leon3 BSP. In general there are two approaches that the workaround uses: A) avoid ECC restarting the RETT instruction B) avoid returning from trap to a JMPL instruction Where A) comes at a higher performance cost than B), so B) is used where posssible. B) can be achived for certain returns from trap handlers if trap entry is controlled by assembly, such as system calls. A) A special JMPL/RETT sequence where instruction cache is disabled temporarily to avoid RETT containing ECC errors, and reading of RETT source registers to "clean" them from incorrect ECC just before RETT is executed. B) The work around prevents JMPL after system calls (TA instruction) and modifies assembly code on return from traps jumping back to application code. Note that for some traps the trapped instruction is always re-executed and can therefore not trigger the errata, for example the SAVE instruction causing window overflow or an float instruction causing FPU disabled trap. RTEMS SPARC traps workaround implementation: NAME NOTE TRAP COMMENT * window overflow 1 - 0x05 always returns to a SAVE * window underflow 1 - 0x06 always returns to a RESTORE * interrupt traps 2 - 0x10..1f special rett sequence workaround * syscall 3 - 0x80 shutdown system - never returns * ABI flush windows 2 - 0x83 special rett sequence workaround * sparc_disable_interrupts 4 - 0x80 * sparc_enable_interrupts 4 - 0x8A * syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction Notes: 1) no workaround needed because trap always returns to non-JMPL instruction 2) workaround implemented by special rett sequence 3) no workaround needed because system call never returns 4) workaround implemented by inserting NOP in system call generation. Thus fall into 1) when workaround is enabled and no trap handler fix needed. Any custom trap handlers may also have to be updated. To simplify that, helper work around assembly code in macros are available in a separate include file <rtems/score/grlib-tn-0018.h>.
Diffstat (limited to 'cpukit/score/cpu/sparc/Makefile.am')
-rw-r--r--cpukit/score/cpu/sparc/Makefile.am2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/score/cpu/sparc/Makefile.am b/cpukit/score/cpu/sparc/Makefile.am
index 6d4c4aead1..714d2e1c1b 100644
--- a/cpukit/score/cpu/sparc/Makefile.am
+++ b/cpukit/score/cpu/sparc/Makefile.am
@@ -9,7 +9,7 @@ include_rtems_HEADERS = rtems/asm.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS = rtems/score/sparc.h rtems/score/cpu.h \
- rtems/score/types.h
+ rtems/score/types.h rtems/score/grlib-tn-0018.h
noinst_LIBRARIES = libscorecpu.a
libscorecpu_a_SOURCES = cpu.c cpu_asm.S