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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-22 07:46:56 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-28 09:26:19 +0200 |
| commit | b2ec2d15971503466e1debf596dc84b6af0f9b13 (patch) | |
| tree | 9c5ccc58cf5c957d5c21f36cd1eb5a73e899b377 /doc | |
| parent | e5120a566c432dbe2c29acc7e02131896d827c5f (diff) | |
sparc: Optimize context switch
The registers g2 through g4 are reserved for applications. GCC uses
them as volatile registers by default. So they are treated like
volatile registers in RTEMS as well.
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/cpu_supplement/sparc.t | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t index 616f79f5c2..320c250e40 100644 --- a/doc/cpu_supplement/sparc.t +++ b/doc/cpu_supplement/sparc.t @@ -397,6 +397,9 @@ describes the role of each of these registers: @end html @end ifset +The registers g2 through g4 are reserved for applications. GCC uses them as +volatile registers by default. So they are treated like volatile registers in +RTEMS as well. @subsubsection Floating Point Registers |