diff options
author | Gedare Bloom <gedare@rtems.org> | 2023-07-25 15:00:29 -0600 |
---|---|---|
committer | Gedare Bloom <gedare@rtems.org> | 2023-07-25 15:04:38 -0600 |
commit | ba02403b951299077233fed1e05ff685bf53cc05 (patch) | |
tree | b1f40881e9646a91b454ab1990bc859337297a1a | |
parent | c48c7d6f88836cefc786a4ba3bb85a3a20200e01 (diff) |
score/aarch64: style fixesaarch64-reformat
-rw-r--r-- | cpukit/score/cpu/aarch64/aarch64-exception-default.c | 22 | ||||
-rw-r--r-- | cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c | 155 | ||||
-rw-r--r-- | cpukit/score/cpu/aarch64/aarch64-thread-idle.c | 2 | ||||
-rw-r--r-- | cpukit/score/cpu/aarch64/cpu.c | 61 |
4 files changed, 132 insertions, 108 deletions
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-default.c b/cpukit/score/cpu/aarch64/aarch64-exception-default.c index f1591cbd5d..df15193996 100644 --- a/cpukit/score/cpu/aarch64/aarch64-exception-default.c +++ b/cpukit/score/cpu/aarch64/aarch64-exception-default.c @@ -46,9 +46,9 @@ #include <rtems/score/cpu.h> #include <rtems/score/percpu.h> -void _AArch64_Exception_default( CPU_Exception_frame *frame ) +void _AArch64_Exception_default(CPU_Exception_frame *frame) { - uint64_t EC = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome ); + uint64_t EC = AARCH64_ESR_EL1_EC_GET(frame->register_syndrome); /* Emulate FPSR flags for FENV if a FPU exception occurred */ if ( EC == 0x2c ) { @@ -59,19 +59,19 @@ void _AArch64_Exception_default( CPU_Exception_frame *frame ) * functions executed in that context will need this information to be * accurate. */ - uint64_t ISS = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome ); + uint64_t ISS = AARCH64_ESR_EL1_EC_GET(frame->register_syndrome); /* If the exception bits are valid, use them */ - if ( ( ISS & ( 1 << 23 ) ) != 0 ) { + if ( (ISS & (1 << 23)) != 0 ) { /* The bits of the lower byte match the FPSR exception bits */ - frame->register_fpsr |= ( ISS & 0xff ); + frame->register_fpsr |= (ISS & 0xff); } } - rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame ); + rtems_fatal(RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame); } -void _CPU_Exception_disable_thread_dispatch( void ) +void _CPU_Exception_disable_thread_dispatch(void) { Per_CPU_Control *cpu_self = _Per_CPU_Get(); @@ -88,9 +88,9 @@ void _AArch64_Exception_frame_copy( *new_ef = *old_ef; } -int _CPU_Exception_frame_get_signal( CPU_Exception_frame *ef ) +int _CPU_Exception_frame_get_signal(CPU_Exception_frame *ef) { - uint64_t EC = AARCH64_ESR_EL1_EC_GET( ef->register_syndrome ); + uint64_t EC = AARCH64_ESR_EL1_EC_GET(ef->register_syndrome); switch ( EC ) { case 0x1: /* WFI */ @@ -115,13 +115,13 @@ int _CPU_Exception_frame_get_signal( CPU_Exception_frame *ef ) } } -void _CPU_Exception_frame_set_resume( CPU_Exception_frame *ef, void *address ) +void _CPU_Exception_frame_set_resume(CPU_Exception_frame *ef, void *address) { ef->register_pc = address; } #define AARCH64_INSTRUCTION_SIZE 4 -void _CPU_Exception_frame_make_resume_next_instruction( CPU_Exception_frame *ef ) +void _CPU_Exception_frame_make_resume_next_instruction(CPU_Exception_frame *ef) { ef->register_pc += AARCH64_INSTRUCTION_SIZE; } diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c index c5b477c72f..e0fbab68dc 100644 --- a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c +++ b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c @@ -44,37 +44,37 @@ #include <inttypes.h> +#include <rtems/bspIo.h> #include <rtems/score/cpu.h> #include <rtems/score/io.h> -#include <rtems/bspIo.h> typedef struct { - char *s; - size_t n; + char *s; + size_t n; } String_Context; -static void _CPU_Put_char( int c, void *arg ) +static void _CPU_Put_char(int c, void *arg) { String_Context *sctx = arg; - size_t n = sctx->n; + size_t n = sctx->n; - if (n > 0) { + if ( n > 0 ) { char *s = sctx->s; - *s = (char) c; + *s = (char) c; sctx->s = s + 1; sctx->n = n - 1; } } static void _CPU_Binary_sprintf( - char *s, - size_t maxlen, + char *s, + size_t maxlen, uint32_t num_bits, uint32_t value ) { String_Context sctx; - uint32_t mask; + uint32_t mask; sctx.s = s; sctx.n = maxlen; @@ -82,14 +82,14 @@ static void _CPU_Binary_sprintf( mask = 1 << (num_bits - 1); while ( mask != 0 ) { - _IO_Printf( _CPU_Put_char, &sctx, "%d", (value & mask ? 1 : 0) ); + _IO_Printf(_CPU_Put_char, &sctx, "%d", (value & mask ? 1 : 0)); mask >>= 1; } s[num_bits] = '\0'; } -static const char* _CPU_Exception_class_to_string( uint16_t exception_class ) +static const char *_CPU_Exception_class_to_string(uint16_t exception_class) { /* The 80 character limit is intentionally ignored for these strings. */ switch ( exception_class ) { @@ -142,82 +142,107 @@ static const char* _CPU_Exception_class_to_string( uint16_t exception_class ) } } -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) +void _CPU_Exception_frame_print(const CPU_Exception_frame *frame) { - uint32_t ec; - uint32_t il; - uint32_t iss; - char ec_str[7]; - char iss_str[26]; - int i; + uint32_t ec; + uint32_t il; + uint32_t iss; + char ec_str[7]; + char iss_str[26]; + int i; const uint128_t *qx; printk( "\n" - "X0 = 0x%016" PRIx64 " X17 = 0x%016" PRIx64 "\n" - "X1 = 0x%016" PRIx64 " X18 = 0x%016" PRIx64 "\n" - "X2 = 0x%016" PRIx64 " X19 = 0x%016" PRIx64 "\n" - "X3 = 0x%016" PRIx64 " X20 = 0x%016" PRIx64 "\n" - "X4 = 0x%016" PRIx64 " X21 = 0x%016" PRIx64 "\n" - "X5 = 0x%016" PRIx64 " X22 = 0x%016" PRIx64 "\n" - "X6 = 0x%016" PRIx64 " X23 = 0x%016" PRIx64 "\n" - "X7 = 0x%016" PRIx64 " X24 = 0x%016" PRIx64 "\n" - "X8 = 0x%016" PRIx64 " X25 = 0x%016" PRIx64 "\n" - "X9 = 0x%016" PRIx64 " X26 = 0x%016" PRIx64 "\n" - "X10 = 0x%016" PRIx64 " X27 = 0x%016" PRIx64 "\n" - "X11 = 0x%016" PRIx64 " X28 = 0x%016" PRIx64 "\n" - "X12 = 0x%016" PRIx64 " FP = 0x%016" PRIx64 "\n" - "X13 = 0x%016" PRIx64 " LR = 0x%016" PRIxPTR "\n" - "X14 = 0x%016" PRIx64 " SP = 0x%016" PRIxPTR "\n" - "X15 = 0x%016" PRIx64 " PC = 0x%016" PRIxPTR "\n" - "X16 = 0x%016" PRIx64 " DAIF = 0x%016" PRIx64 "\n" + "X0 = 0x%016" PRIx64 " X17 = 0x%016" PRIx64 "\n" + "X1 = 0x%016" PRIx64 " X18 = 0x%016" PRIx64 "\n" + "X2 = 0x%016" PRIx64 " X19 = 0x%016" PRIx64 "\n" + "X3 = 0x%016" PRIx64 " X20 = 0x%016" PRIx64 "\n" + "X4 = 0x%016" PRIx64 " X21 = 0x%016" PRIx64 "\n" + "X5 = 0x%016" PRIx64 " X22 = 0x%016" PRIx64 "\n" + "X6 = 0x%016" PRIx64 " X23 = 0x%016" PRIx64 "\n" + "X7 = 0x%016" PRIx64 " X24 = 0x%016" PRIx64 "\n" + "X8 = 0x%016" PRIx64 " X25 = 0x%016" PRIx64 "\n" + "X9 = 0x%016" PRIx64 " X26 = 0x%016" PRIx64 "\n" + "X10 = 0x%016" PRIx64 " X27 = 0x%016" PRIx64 "\n" + "X11 = 0x%016" PRIx64 " X28 = 0x%016" PRIx64 "\n" + "X12 = 0x%016" PRIx64 " FP = 0x%016" PRIx64 "\n" + "X13 = 0x%016" PRIx64 " LR = 0x%016" PRIxPTR "\n" + "X14 = 0x%016" PRIx64 " SP = 0x%016" PRIxPTR "\n" + "X15 = 0x%016" PRIx64 " PC = 0x%016" PRIxPTR "\n" + "X16 = 0x%016" PRIx64 " DAIF = 0x%016" PRIx64 "\n" "VEC = 0x%016" PRIxPTR " CPSR = 0x%016" PRIx64 "\n", - frame->register_x0, frame->register_x17, - frame->register_x1, frame->register_x18, - frame->register_x2, frame->register_x19, - frame->register_x3, frame->register_x20, - frame->register_x4, frame->register_x21, - frame->register_x5, frame->register_x22, - frame->register_x6, frame->register_x23, - frame->register_x7, frame->register_x24, - frame->register_x8, frame->register_x25, - frame->register_x9, frame->register_x26, - frame->register_x10, frame->register_x27, - frame->register_x11, frame->register_x28, - frame->register_x12, frame->register_fp, - frame->register_x13, (intptr_t) frame->register_lr, - frame->register_x14, (intptr_t) frame->register_sp, - frame->register_x15, (intptr_t) frame->register_pc, - frame->register_x16, frame->register_daif, - (intptr_t) frame->vector, frame->register_cpsr + frame->register_x0, + frame->register_x17, + frame->register_x1, + frame->register_x18, + frame->register_x2, + frame->register_x19, + frame->register_x3, + frame->register_x20, + frame->register_x4, + frame->register_x21, + frame->register_x5, + frame->register_x22, + frame->register_x6, + frame->register_x23, + frame->register_x7, + frame->register_x24, + frame->register_x8, + frame->register_x25, + frame->register_x9, + frame->register_x26, + frame->register_x10, + frame->register_x27, + frame->register_x11, + frame->register_x28, + frame->register_x12, + frame->register_fp, + frame->register_x13, + (intptr_t) frame->register_lr, + frame->register_x14, + (intptr_t) frame->register_sp, + frame->register_x15, + (intptr_t) frame->register_pc, + frame->register_x16, + frame->register_daif, + (intptr_t) frame->vector, + frame->register_cpsr ); - ec = frame->register_syndrome >> 26 & 0x3f; - il = frame->register_syndrome >> 25 & 0x1; + ec = frame->register_syndrome >> 26 & 0x3f; + il = frame->register_syndrome >> 25 & 0x1; iss = frame->register_syndrome & 0x1ffffff; - _CPU_Binary_sprintf( ec_str, sizeof( ec_str ), sizeof( ec_str ) - 1, ec ); - _CPU_Binary_sprintf( iss_str, sizeof( iss_str ), sizeof( iss_str ) - 1, iss ); + _CPU_Binary_sprintf(ec_str, sizeof(ec_str), sizeof(ec_str) - 1, ec); + _CPU_Binary_sprintf(iss_str, sizeof(iss_str), sizeof(iss_str) - 1, iss); printk( - "ESR = EC: 0b%s" " IL: 0b%d" " ISS: 0b%s" "\n" + "ESR = EC: 0b%s" + " IL: 0b%d" + " ISS: 0b%s" + "\n" " %s\n", - ec_str, il, iss_str, _CPU_Exception_class_to_string( ec ) + ec_str, + il, + iss_str, + _CPU_Exception_class_to_string(ec) ); - printk( "FAR = 0x%016" PRIx64 "\n", frame->register_fault_address ); + printk("FAR = 0x%016" PRIx64 "\n", frame->register_fault_address); qx = &frame->register_q0; printk( "FPCR = 0x%016" PRIx64 " FPSR = 0x%016" PRIx64 "\n", - frame->register_fpcr, frame->register_fpsr + frame->register_fpcr, + frame->register_fpsr ); - for ( i = 0 ; i < 32 ; ++i ) { - uint64_t low = (uint64_t) qx[i]; + for ( i = 0; i < 32; ++i ) { + uint64_t low = (uint64_t) qx[i]; uint64_t high = (uint64_t) (qx[i] >> 64); - printk( "Q%02i = 0x%016" PRIx64 "%016" PRIx64 "\n", i, high, low ); + printk("Q%02i = 0x%016" PRIx64 "%016" PRIx64 "\n", i, high, low); } } diff --git a/cpukit/score/cpu/aarch64/aarch64-thread-idle.c b/cpukit/score/cpu/aarch64/aarch64-thread-idle.c index ce93b4facd..188ac618d9 100644 --- a/cpukit/score/cpu/aarch64/aarch64-thread-idle.c +++ b/cpukit/score/cpu/aarch64/aarch64-thread-idle.c @@ -38,7 +38,7 @@ #include <rtems/score/cpu.h> -void *_CPU_Thread_Idle_body( uintptr_t ignored ) +void *_CPU_Thread_Idle_body(uintptr_t ignored) { while ( true ) { __asm__ volatile ("wfi"); diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c index 207508302b..e8b68f7bbe 100644 --- a/cpukit/score/cpu/aarch64/cpu.c +++ b/cpukit/score/cpu/aarch64/cpu.c @@ -71,66 +71,65 @@ #endif RTEMS_STATIC_ASSERT( - sizeof( CPU_Exception_frame ) == AARCH64_EXCEPTION_FRAME_SIZE, + sizeof(CPU_Exception_frame) == AARCH64_EXCEPTION_FRAME_SIZE, AARCH64_EXCEPTION_FRAME_SIZE ); RTEMS_STATIC_ASSERT( - sizeof( CPU_Exception_frame ) % CPU_STACK_ALIGNMENT == 0, + sizeof(CPU_Exception_frame) % CPU_STACK_ALIGNMENT == 0, CPU_Exception_frame_alignment ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, register_sp ) - == AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET, + offsetof(CPU_Exception_frame, register_sp) == + AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, register_lr ) - == AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET, + offsetof(CPU_Exception_frame, register_lr) == + AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, register_daif ) - == AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET, + offsetof(CPU_Exception_frame, register_daif) == + AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, register_syndrome ) - == AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET, + offsetof(CPU_Exception_frame, register_syndrome) == + AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, vector ) - == AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET, + offsetof(CPU_Exception_frame, vector) == + AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, register_fpsr ) - == AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET, + offsetof(CPU_Exception_frame, register_fpsr) == + AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET ); RTEMS_STATIC_ASSERT( - offsetof( CPU_Exception_frame, register_q0 ) - == AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET, + offsetof(CPU_Exception_frame, register_q0) == + AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET, AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET ); - void _CPU_Context_Initialize( Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint64_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area + void *stack_area_begin, + size_t stack_area_size, + uint64_t new_level, + void (*entry_point)(void), + bool is_fp, + void *tls_area ) { (void) new_level; @@ -142,11 +141,11 @@ void _CPU_Context_Initialize( the_context->thread_id = (uintptr_t) tls_area; if ( tls_area != NULL ) { - the_context->thread_id = (uintptr_t) _TLS_Initialize_area( tls_area ); + the_context->thread_id = (uintptr_t) _TLS_Initialize_area(tls_area); } } -void _CPU_ISR_Set_level( uint32_t level ) +void _CPU_ISR_Set_level(uint32_t level) { /* Set the mask bit if interrupts are disabled */ if ( level ) { @@ -162,7 +161,7 @@ void _CPU_ISR_Set_level( uint32_t level ) } } -uint32_t _CPU_ISR_Get_level( void ) +uint32_t _CPU_ISR_Get_level(void) { uint64_t level; @@ -171,23 +170,23 @@ uint32_t _CPU_ISR_Get_level( void ) : [level] "=&r" (level) ); - return ( level & AARCH64_PSTATE_I ) != 0; + return (level & AARCH64_PSTATE_I) != 0; } -void _CPU_Initialize( void ) +void _CPU_Initialize(void) { /* Do nothing */ } -void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) +void _CPU_Fatal_halt(uint32_t source, CPU_Uint32ptr error) { ISR_Level level; - _CPU_ISR_Disable( level ); + _CPU_ISR_Disable(level); (void) level; __asm__ volatile ("mov x0, %0\n" : "=r" (error) : "0" (error) : "x0" ); - while (1); + while ( 1 ); } |