| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-09-09 | Map RISC-V FPU CSR on host cpu using fenv.h | Jiri Gaisler |
| 2020-02-29 | Update to version 2.212.21 | Jiri Gaisler |
| 2019-11-09 | Support building on MinGW-W64/MSYS22.19 | Jiri Gaisler |
| 2019-07-02 | Make readline conditional and add linenoise it not present. | Chris Johns |
| 2019-05-28 | Made L1 cache optional through --enable-l1cache | Jiri Gaisler |
| 2019-05-14 | Standalone sis - initial commit | Jiri Gaisler |
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index : sis.git | |
| Clone of master repository. | Charlie & |
| summaryrefslogtreecommitdiff |