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SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
brief: |
SIS is a SPARC V7/V8 and RISC-V RV32IMACFD architecture simulator.
copyrights:
- Copyright (C) 2023 embedded brains GmbH & Co. KG
enabled-by:
and:
- sparc/gr712rc
- target/simulator
description:
The ``gr712rc`` configuration of ${/glossary/sis:/term} simulates a
configurable amount of LEON3 ${/glossary/sparc:/term} V8 cores and a subset
of the ${/glossary/gr712rc:/term} peripherals.
links:
- role: requirement-refinement
uid: ../gr712rc
name: SIS configured to simulate the GR712RC
non-functional-type: design-target
rationale: null
references: []
requirement-type: non-functional
text: |
The ${.:/name} shall be a ${/glossary/target:/term}.
type: requirement
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