diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h index bca7058112..77f2921401 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h @@ -34,6 +34,7 @@ extern "C" { #if defined (ADC1) || defined (ADC2) || defined (ADC3) /** @defgroup ADC_LL ADC + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -42,6 +43,7 @@ extern "C" { /* Private constants ---------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -402,6 +404,7 @@ extern "C" { */ /** @defgroup ADC_LL_Alias_definition ADC Alias definition + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_SetChannelPreSelection LL_ADC_SetChannelPreselection /* Alias of LL_ADC_SetChannelPreselection for backward compatibility. */ @@ -412,6 +415,7 @@ extern "C" { /* Private macros ------------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -434,6 +438,7 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -627,10 +632,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup ADC_LL_EC_FLAG ADC flags + * @ingroup RTEMSBSPsARMSTM32H7 * @brief Flags defines which can be used with LL_ADC_ReadReg function * @{ */ @@ -673,6 +680,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @ingroup RTEMSBSPsARMSTM32H7 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions * @{ */ @@ -692,6 +700,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /* List of ADC registers intended to be used (most commonly) with */ @@ -704,6 +713,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ @@ -726,6 +736,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /* Note: Other measurement paths to internal channels may be available */ @@ -742,6 +753,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL) /*!< Boost mode is configured for frequency <= 6.25Mhz */ @@ -754,6 +766,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */ @@ -764,6 +777,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1) /*!< ADC calibration linearity word 1 */ @@ -777,6 +791,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */ @@ -806,6 +821,7 @@ typedef struct #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ @@ -817,6 +833,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */ @@ -840,6 +857,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ @@ -849,6 +867,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ @@ -860,6 +879,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */ @@ -869,6 +889,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */ @@ -878,6 +899,7 @@ typedef struct */ #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */ @@ -887,6 +909,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ @@ -896,6 +919,7 @@ typedef struct */ #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */ @@ -908,6 +932,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ @@ -918,6 +943,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ @@ -967,6 +993,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ @@ -1002,6 +1029,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ @@ -1012,6 +1040,7 @@ typedef struct */ #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. On devices STM32H72xx and STM32H73xx */ @@ -1026,6 +1055,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ @@ -1035,6 +1065,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */ @@ -1047,6 +1078,7 @@ typedef struct #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -1059,6 +1091,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ @@ -1068,6 +1101,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ @@ -1091,6 +1125,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ @@ -1107,6 +1142,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ @@ -1130,6 +1166,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */ @@ -1163,6 +1200,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ @@ -1173,6 +1211,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ @@ -1182,6 +1221,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ @@ -1192,6 +1232,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ @@ -1203,6 +1244,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ @@ -1212,6 +1254,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ @@ -1223,6 +1266,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycles */ @@ -1238,6 +1282,7 @@ typedef struct */ #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */ @@ -1254,6 +1299,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ @@ -1264,6 +1310,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ @@ -1274,6 +1321,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ @@ -1360,6 +1408,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */ @@ -1369,6 +1418,7 @@ typedef struct */ #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ @@ -1385,6 +1435,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ @@ -1397,6 +1448,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ @@ -1406,6 +1458,7 @@ typedef struct */ #if defined(ADC_VER_V5_V90) /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ @@ -1422,6 +1475,7 @@ typedef struct #endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ @@ -1441,6 +1495,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ @@ -1456,6 +1511,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ @@ -1466,6 +1522,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */ @@ -1486,6 +1543,7 @@ typedef struct */ /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ @@ -1498,6 +1556,7 @@ typedef struct /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @ingroup RTEMSBSPsARMSTM32H7 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code @@ -1571,10 +1630,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -1599,6 +1660,7 @@ typedef struct */ /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -2556,10 +2618,12 @@ typedef struct /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -2616,6 +2680,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis */ /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -2812,6 +2877,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy */ /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -3800,6 +3866,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse */ /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -4587,6 +4654,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) */ /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -5308,6 +5376,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, */ /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -5630,6 +5699,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t */ /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -6244,6 +6314,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, */ /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -6467,6 +6538,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) */ /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @@ -6755,6 +6827,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -6992,6 +7065,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) */ /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -7187,6 +7261,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef */ /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -7426,6 +7501,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -7957,6 +8033,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_ */ /** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -8340,6 +8417,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ |