diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h index 2b63e8f33d..68794e586a 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h @@ -47,6 +47,7 @@ extern "C" { */ /** @defgroup CORTEX_LL CORTEX + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -60,10 +61,12 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/ @@ -73,6 +76,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ @@ -85,6 +89,7 @@ extern "C" { #if __MPU_PRESENT /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */ @@ -96,6 +101,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */ @@ -121,6 +127,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ @@ -156,6 +163,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/ @@ -169,6 +177,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ @@ -182,6 +191,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */ @@ -191,6 +201,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ @@ -200,6 +211,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ @@ -209,6 +221,7 @@ extern "C" { */ /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ @@ -225,10 +238,12 @@ extern "C" { /* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -303,6 +318,7 @@ __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) */ /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -381,6 +397,7 @@ __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) */ /** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -419,6 +436,7 @@ __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) */ /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -478,6 +496,7 @@ __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) #if __MPU_PRESENT /** @defgroup CORTEX_LL_EF_MPU MPU + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ |