diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h index 5e8a401e77..32bbb4e753 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h @@ -171,6 +171,7 @@ extern "C" { /* Exported typedef ----------------------------------------------------------*/ /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -451,10 +452,12 @@ typedef struct */ /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NORSRAM_BANK1 (0x00000000U) @@ -466,6 +469,7 @@ typedef struct */ /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) @@ -475,6 +479,7 @@ typedef struct */ /** @defgroup FMC_Memory_Type FMC Memory Type + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_MEMORY_TYPE_SRAM (0x00000000U) @@ -485,6 +490,7 @@ typedef struct */ /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) @@ -495,6 +501,7 @@ typedef struct */ /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) @@ -504,6 +511,7 @@ typedef struct */ /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) @@ -513,6 +521,7 @@ typedef struct */ /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) @@ -522,6 +531,7 @@ typedef struct */ /** @defgroup FMC_Wait_Timing FMC Wait Timing + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) @@ -531,6 +541,7 @@ typedef struct */ /** @defgroup FMC_Write_Operation FMC Write Operation + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) @@ -540,6 +551,7 @@ typedef struct */ /** @defgroup FMC_Wait_Signal FMC Wait Signal + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) @@ -549,6 +561,7 @@ typedef struct */ /** @defgroup FMC_Extended_Mode FMC Extended Mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) @@ -558,6 +571,7 @@ typedef struct */ /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) @@ -567,6 +581,7 @@ typedef struct */ /** @defgroup FMC_Page_Size FMC Page Size + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_PAGE_SIZE_NONE (0x00000000U) @@ -580,6 +595,7 @@ typedef struct */ /** @defgroup FMC_Write_Burst FMC Write Burst + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_WRITE_BURST_DISABLE (0x00000000U) @@ -589,6 +605,7 @@ typedef struct */ /** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) @@ -599,6 +616,7 @@ typedef struct #if defined(FMC_BCR1_WFDIS) /** @defgroup FMC_Write_FIFO FMC Write FIFO + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS @@ -609,6 +627,7 @@ typedef struct */ /** @defgroup FMC_Access_Mode FMC Access Mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_ACCESS_MODE_A (0x00000000U) @@ -625,9 +644,11 @@ typedef struct /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_NAND_Bank FMC NAND Bank + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NAND_BANK3 (0x00000100U) @@ -636,6 +657,7 @@ typedef struct */ /** @defgroup FMC_Wait_feature FMC Wait feature + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) @@ -645,6 +667,7 @@ typedef struct */ /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) @@ -653,6 +676,7 @@ typedef struct */ /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) @@ -662,6 +686,7 @@ typedef struct */ /** @defgroup FMC_ECC FMC ECC + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NAND_ECC_DISABLE (0x00000000U) @@ -671,6 +696,7 @@ typedef struct */ /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) @@ -688,9 +714,11 @@ typedef struct */ /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_BANK1 (0x00000000U) @@ -700,6 +728,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) @@ -711,6 +740,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) @@ -721,6 +751,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) @@ -731,6 +762,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) @@ -740,6 +772,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) @@ -750,6 +783,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) @@ -759,6 +793,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) @@ -769,6 +804,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_RBURST_DISABLE (0x00000000U) @@ -778,6 +814,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) @@ -788,6 +825,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) @@ -802,6 +840,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 @@ -812,6 +851,7 @@ typedef struct */ /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_SDRAM_NORMAL_MODE (0x00000000U) @@ -827,6 +867,7 @@ typedef struct /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_IT_RISING_EDGE (0x00000008U) @@ -838,6 +879,7 @@ typedef struct */ /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define FMC_FLAG_RISING_EDGE (0x00000001U) @@ -861,6 +903,7 @@ typedef struct /* Private macro -------------------------------------------------------------*/ /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @@ -875,6 +918,7 @@ typedef struct */ #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros + * @ingroup RTEMSBSPsARMSTM32H7 * @brief macros to handle NOR device enable/disable and read/write operations * @{ */ @@ -902,6 +946,7 @@ typedef struct */ /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros + * @ingroup RTEMSBSPsARMSTM32H7 * @brief macros to handle NAND device enable/disable * @{ */ @@ -926,6 +971,7 @@ typedef struct */ /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @ingroup RTEMSBSPsARMSTM32H7 * @brief macros to handle NAND interrupts * @{ */ @@ -987,6 +1033,7 @@ typedef struct /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt + * @ingroup RTEMSBSPsARMSTM32H7 * @brief macros to handle SDRAM interrupts * @{ */ @@ -1046,13 +1093,16 @@ typedef struct /* Private functions ---------------------------------------------------------*/ /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_LL_NORSRAM NOR SRAM + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, @@ -1069,6 +1119,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, */ /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); @@ -1081,9 +1132,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic */ /** @defgroup FMC_LL_NAND NAND + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); @@ -1097,6 +1150,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); @@ -1112,9 +1166,11 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** @defgroup FMC_LL_SDRAM SDRAM + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); @@ -1126,6 +1182,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); */ /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions + * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); |